Debug hooks
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February 28, 2007
Published by Gary Stringham at February 28, 2007
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After a presentation I gave at a conference, one of the attendees came up and told me about his ASIC design team that consisted of young engineers. They had completed their design and told him that they were done. He then asked the question, “Six months from now when you […]
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January 31, 2008
Published by Gary Stringham at January 31, 2008
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A client recently asked me to write down some suggestions of best practices and process improvements for his company. I noted several suggestions, sorted them into four categories, and started writing them up. Partway through this process, I noticed that two of my recommendations seemed to contradict each other. On […]
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July 14, 2010
Published by Gary Stringham at July 14, 2010
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A comment in the GABEonEDA blog entry “Accellera Works Toward a Unified Verification Methodology (UVM)” recently caught my attention: Silicon respins due to design errors not only have not diminished in number, they have actually increased. This is an indication that complexity has grown more than the ability of verification […]
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