Reviews of
Register Design Tools
Register Design Tools are tools that generate hardware,
firmware, and documentation files from one register design file. These tools align with
our efforts to improve collaboration between hardware and firmware teams,
helping them to more effectively develop embedded products.
Read this book excerpt for a discussion on the benefits of this type of tool.
We are promoting this growing market niche from several angles, including
providing the following informational resources:
- Free table comparing features. (Under development. See below.)
- Free interviews with the companies regarding their respective products. (Under development.)
- In-depth analysis of the products. (Future development.)
- Analysis of how well the products support our best practices. (Future development.)
The following comparison table will be filled in as data is gathered:
Product |
| Version |
1.11 |
|
10/24/2011 |
1.32 |
|
|
|
464 |
| Webpage |
Link |
Link2 |
Link |
Link |
Link |
Link |
Link |
Link |
| Vendor |
Duolog Technologies |
Cadence |
Semifore, Inc. |
Chuck Benz ASIC and FPGA Design |
Atrenta |
Agnisys Inc. |
PDTi |
Veripool |
| Product type |
Commercial |
Commercial |
Commercial |
Open Source |
Commercial |
Commercial |
Commercial |
Open Source |
| Interview |
Interview |
|
Interview |
|
|
Interview |
Interview |
Interview |
System Specifications |
| Tool Location |
| Local |
Yes |
TBD |
Yes |
Yes |
TBD |
TBD |
TBD |
Yes |
| Client/server |
Yes |
|
Yes |
|
|
|
|
|
| Server |
Yes |
|
Yes |
|
|
|
|
|
| Private cloud |
|
|
|
|
|
|
|
|
| Public cloud |
Yes |
|
|
|
|
|
|
|
| Operating System |
| Windows |
XP, Windows 7 |
|
XP, Vista, 7 |
Any |
|
|
|
Any |
| Linux |
Redhat
Centos
Suse
Ubuntu |
|
Red Hat 4, 5, 6
Centos 4, 5, 6
Suse 10,11 |
Any |
|
|
|
Any |
| Cloud |
|
|
|
|
|
|
|
|
| Other |
|
|
|
Any OS with Perl |
|
|
|
Any OS with Perl |
| Licensing |
| Open source |
|
|
|
Yes |
|
|
|
Yes |
| One per site |
Yes |
|
Yes |
|
|
|
|
|
| One per seat |
Yes |
|
|
|
|
|
|
|
| Design size |
Yes |
|
|
|
|
|
|
|
| Trial Available |
Yes |
|
Yes |
|
|
|
|
|
| Other |
|
|
|
|
|
|
|
GPL or Perl Artistic |
Using the Tool |
| Primary User Interface |
| Text editor |
Yes |
TBD |
Yes |
Yes |
TBD |
TBD |
TBD |
Yes |
| Vendor GUI |
Yes |
|
|
|
|
|
|
|
| Third-party tool |
Yes |
|
Yes |
|
|
|
|
Yes |
| Browser |
|
|
|
|
|
|
|
|
| Register Design Files |
| Plain text or binary |
Plain text |
|
Plain text |
Plain text |
|
|
|
Plain text |
| File format name |
XML |
|
CSRSpec, SystemRDL,
IP-XACT, CSV |
csrGen format,
.csrs extension |
|
|
|
.vregs |
| Format basis |
IP-XACT XML |
|
CSRSpec is a superset |
Developed for csrGen, includes some verilog |
|
|
|
Internal format |
| Version controllable |
Yes3 |
|
Yes |
Yes |
|
|
|
Yes |
| Diffable |
Yes3 |
|
Yes |
Yes |
|
|
|
Yes |
Register Design |
| Architecture |
| Hierarchy |
Yes |
TBD |
Yes |
|
TBD |
TBD |
TBD |
Yes |
| Multiple instantiations |
Yes |
|
Yes |
Yes |
|
|
|
Yes |
| Parameterized instantiations |
Yes |
|
Yes |
|
|
|
|
Yes |
| Multi-core |
Yes |
|
Yes |
|
|
|
|
Yes |
| Bit Fields |
| Supported bit types |
Yes |
|
Yes |
Yes |
|
|
|
Yes |
| Specify bit width |
Yes |
|
Yes |
Yes |
|
|
|
Yes |
| Reset value |
Yes |
|
Yes |
Yes |
|
|
|
Yes |
| Registers |
| Data bus width |
Yes |
|
Yes |
Yes |
|
|
|
|
| Specify bit types and mix |
Yes |
|
Yes |
Yes |
|
|
|
Yes |
| Multi-core assignments |
Yes |
|
Yes |
|
|
|
|
|
| Documentation |
| Long text |
Yes |
|
Yes |
Yes |
|
|
|
Yes |
| Text formatting |
Yes |
|
Yes |
|
|
|
|
Yes |
| Extended character sets |
Yes |
|
|
|
|
|
|
Yes |
| Tables |
Yes |
|
Yes |
|
|
|
|
Yes |
| Objects |
Yes |
|
Yes |
|
|
|
|
Yes |
Process Files |
| How? |
| Within editor application |
Yes |
TBD |
Yes |
|
TBD |
TBD |
TBD |
|
| Separate application |
|
|
|
|
|
|
|
|
| Command line |
Yes |
|
Yes |
Yes |
|
|
|
Yes |
| Batch |
Yes |
|
Yes |
|
|
|
|
|
| Build Specification |
| Subset build |
Yes |
|
Yes |
|
|
|
|
|
| Make-like facility |
|
|
Yes |
|
|
|
|
Yes |
| Documentation contents |
Yes |
|
Yes |
|
|
|
|
Yes |
| Error Checking |
| Real-time checking |
Yes |
|
|
|
|
|
|
|
| Compile-time checking |
Yes |
|
Yes |
Yes |
|
|
|
Yes |
| Error details |
Yes |
|
Yes |
|
|
|
|
Yes |
| Attempts to keep processing |
Yes |
|
Yes |
Limited |
|
|
|
Yes |
| Context-sensitive help |
Yes |
|
|
|
|
|
|
|
Import File Formats |
| Industry Formats |
| IEEE 1685 (IP-XACT) |
Yes |
TBD |
Yes |
|
TBD |
TBD |
TBD |
|
| SystemRDL |
Yes |
|
Yes |
|
|
|
|
|
| XML |
Yes |
|
Yes |
|
|
|
|
Upon request |
| CSV |
Yes |
|
Yes |
|
|
|
|
|
| Competitor's Formats |
| Bitwise |
Yes |
|
|
|
|
|
|
|
| Blueprint |
Upon request |
|
Yes |
|
|
|
|
|
| csrGen |
Upon request |
|
|
Yes |
|
|
|
|
| CSRSpec |
Upon request |
|
Yes |
|
|
|
|
|
| GenSys Registers |
Upon request |
|
|
|
|
|
|
|
| IDesignSpec |
Upon request |
|
|
|
|
|
|
|
| SpectaReg |
Upon request |
|
|
|
|
|
|
|
| Vregs |
Upon request |
|
|
|
|
|
|
Yes |
| Customizable Import |
| User customizable |
Fully user customizable |
|
|
Limited user customizable |
|
|
|
Fully user customizable |
| Leverage built-in parsers |
Yes |
|
|
No |
|
|
|
Yes |
| Learning curve for user |
Easy |
|
|
Hard |
|
|
|
Medium |
| Importing framework |
Ruby, Perl, structured templates |
|
|
Perl |
|
|
|
Perl |
Output File Formats |
| Hardware: Design Formats: |
| Verilog |
Yes |
TBD |
Yes |
Yes |
TBD |
TBD |
TBD |
Yes |
| VHDL |
Yes |
|
Yes |
|
|
|
|
|
| SystemC |
Yes |
|
Yes |
|
|
|
|
Yes |
| SystemVerilog |
Yes |
|
Yes |
|
|
|
|
|
| Hardware: Verification Formats |
| OVM |
Yes |
|
Yes |
|
|
|
|
|
| VVM |
Yes |
|
Yes |
|
|
|
|
|
| UVM |
Yes |
|
Yes |
|
|
|
|
|
| RALF |
Yes |
|
Yes |
|
|
|
|
|
| RAL |
Yes |
|
Yes |
|
|
|
|
|
| openVera |
Upon request |
|
Yes |
|
|
|
|
|
| Others |
|
|
|
|
|
|
|
|
| Hardware: Virtual Prototypes |
| Synopsys Innovator |
|
|
Yes |
|
|
|
|
|
| Hardware: Processor Support |
| X86 |
Yes |
|
Yes |
|
|
|
|
|
| ARM |
Yes |
|
Yes |
|
|
|
|
|
| Hardware: Bus Protocol Support |
| AMBA-AHB |
Yes |
|
Yes |
|
|
|
|
|
| AMBA-APB |
Yes |
|
|
|
|
|
|
|
| AVALON |
Yes |
|
Yes |
|
|
|
|
|
| OCP |
Yes |
|
|
|
|
|
|
|
| Firmware: Languages |
| C |
Yes |
|
Yes |
Yes |
|
|
|
|
| C++ |
Yes |
|
Yes |
|
|
|
|
Yes |
| C# |
Yes |
|
|
|
|
|
|
|
| Java |
Upon request |
|
|
|
|
|
|
|
| Firmware: Operating Systems |
| Windows |
Yes |
|
Yes |
|
|
|
|
|
| WinCE |
Yes |
|
|
|
|
|
|
|
| Linux |
Yes |
|
Yes |
|
|
|
|
|
| Android |
Yes |
|
|
|
|
|
|
|
| Firmware: Processor support |
| X86 |
Yes |
|
|
|
|
|
|
|
| ARM |
Yes |
|
|
|
|
|
|
|
| Documentation Formats |
| HTML |
Yes |
|
Yes |
Yes |
|
|
|
Yes |
| DHTML |
Yes |
|
Yes |
|
|
|
|
|
| PDF |
Yes |
|
|
|
|
|
|
|
| RTF |
Yes |
|
Yes |
|
|
|
|
|
| FrameMaker |
Yes |
|
Yes |
|
|
|
|
Yes |
| MS Word |
Yes |
|
Yes |
|
|
|
|
Yes |
| SVG |
Yes |
|
|
|
|
|
|
|
| DITA |
Yes |
|
Upon request |
|
|
|
|
|
| DocBook XML |
Yes |
|
Yes |
|
|
|
|
|
Export and Customized Output |
| Industry Formats |
| IEEE 1685 (IP-XACT) |
Yes |
TBD |
Yes |
|
TBD |
TBD |
TBD |
|
| SystemRDL |
Yes |
|
Yes |
|
|
|
|
|
| XML |
Yes |
|
Yes |
|
|
|
|
|
| CSV |
Yes |
|
Yes |
|
|
|
|
|
| Competitor's Formats |
| Bitwise |
Yes |
|
|
|
|
|
|
|
| Blueprint |
Upon request |
|
Yes |
|
|
|
|
|
| csrGen |
Upon request |
|
Upon request |
Yes |
|
|
|
|
| CSRSpec |
Upon request |
|
Yes |
|
|
|
|
|
| GenSys Registers |
Upon request |
|
|
|
|
|
|
|
| IDesignSpec |
Upon request |
|
|
|
|
|
|
|
| SpectaReg |
Upon request |
|
|
|
|
|
|
|
| Vregs |
Upon request |
|
Upon request |
|
|
|
|
Yes |
| Customizable Output |
| User customizable |
Fully user customizable |
|
Fully user customizable |
Limited user customizable |
|
|
|
Fully user customizable |
| Leverage built-in generators |
Yes |
|
Yes |
Yes |
|
|
|
Yes |
| Learning curve for user |
Easy |
|
Easy |
Medium |
|
|
|
Medium |
| Exporting framework |
Perl, Ruby, Freemarker templates |
|
Perl |
Perl |
|
|
|
Perl |
Service/Support |
| Service |
| Porting support |
Yes |
TBD |
Yes |
|
TBD |
TBD |
TBD |
|
| Customization support |
Yes |
|
|
|
|
|
|
|
| Methodology consultation |
Yes |
|
|
|
|
|
|
|
| On-site support |
Yes |
|
|
|
|
|
|
|
| Phone support |
Yes |
|
Yes |
|
|
|
|
|
| Email/online-form support |
Yes |
|
Yes |
Yes |
|
|
|
Yes |
| Training/Help |
| Printed manuals/tutorials |
Yes |
|
Yes |
Yes |
|
|
|
|
| Installed help files/tutorials |
Yes |
|
Yes |
|
|
|
|
Yes |
| Online help files/tutorials |
Yes |
|
|
|
|
|
|
Yes |
| Context-sensitive help |
Yes |
|
|
|
|
|
|
|
| Classroom with live instructor |
Yes |
|
|
|
|
|
|
|
| Live webinar |
Yes |
|
|
|
|
|
|
|
| Pre-recorded webinars/videos |
Yes |
|
|
|
|
|
|
|
| Self-paced computer instruction |
|
|
|
|
|
|
|
|
| FAQ |
Yes |
|
|
|
|
|
|
|
| Users forum |
|
|
|
|
|
|
|
Yes |
| Other |
|
|
|
|
|
|
|
|
- All names of the tools are trademarked as indicated by their respective companies.
- Cadence bought Denali which owned Blueprint. This link points to a Denali webpage as Cadence has not yet ported the page to the Cadence domain.
- In addition to using third-party version control and diff tools, this tool has built-in version control and diff capabilities.
Disclaimer: Gary Stringham & Associates is in a non-exclusive partnership agreement
with one or more of these vendors for the purpose of improving and promoting these tools but is not being compensated
for the promotion or sales of these tools.
|
